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Wireless CPU

Q24 Series

General Description

©Confidential Page: 17 / 83

This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without

prior written agreement.

WM_PRJ_Q24NG_PTS_001-004

January 16, 2007

2.2 Functional Architecture

The global architecture of the Wireless CPU

Q24 Series is shown below:

Figure 1: Functional architecture

Power supply

Battery

management

SIM supply

FLASH

RAM

Audio interface

RF interface

A/D converter

SIM controller

CPU

Vocoder

Memory

management

RTC

Keyboard

controller

SPI

–

I2C

Controller

UART1

–

UART2

Controller

Transceiver

PA front-end

module

CONNECTIONS

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